The present invention relates to an error detection and correction system, and more particularly, to a method and apparatus for detecting single bit errors in a string of data bits such that the detected single bit errors may be corrected in an economical and efficient manner.
Error detection and correction circuits are known which detect single and double bit errors in data from a storage device, and for correcting single bit errors in such data. Many of these error detection and correction circuits are based on Hamming code or modified Hamming code described in the publication "Error Detecting and Correcting Codes", R. W. Hamming, The Bell System Journal, Volume XXIX, April, 1950, No. 2, pp. 147-160. Examples of these type devices are disclosed in U.S. Pat. Nos. 3,648,239; 4,005,405; 4,201,337; 4,251,863; and 4,410,988. An LSI device for error detection and correction is described in the publication "Chip Cuts Parts Count in Error Correction Networks", Reinhard Schurba, Electronics, Nov. 9, 1978.
The apparatus disclosed in U.S. Pat. No. 4,251,863 includes means for generating a hold signal to halt the requestor during the time required to test the requested addressable locations in a memory, and to correct an erroneous data word.
U.S. Pat. No. 4,112,502 to Scheuneman discloses apparatus for conditionally bypassing an error correction function wherein if no error exists in the read data from a random access memory, the memory is accessed at a relatively fast access time while, if an error exists in the read data the memory is accessed at a relatively slower access time to provide the added time required by an error correction circuit to correct the read data.
Many devices, such as the device disclosed in U.S. Pat. No. 4,201,337 and the device described in the Schurba article, and the AM2960 cascadable 16 bit Error Detection and Correction Unit available from Advanced Micro Devices Inc. of Sunnyvale, CA 94086, may be configured for error detection and correction of 64 bits. To check 64 bits of data, several of these devices must be cascaded. Error correction and detection devices are expensive, and there is an economic benefit in limiting the number of these devices needed to detect and correct errors in 64 bits of data.
In many configurations, a data processing system will assume that data from the memory is correct, and will continue processing until an error is detected. If a correctable error is found, the processing is halted, corrected data is substituted for the bad data, and processing is resumed. If the error detection process takes too long, then errors caused by the processing of bad data must also be located and corrected, if possible. Thus, it is important to locate errors in data as soon as possible so that processing may be stopped before the bad data is used.
In the present invention, data may be fetched from the memory either in 32 bit data fields, or as 64 bits of instruction data in two 32 bit portions. Each portion of the data is checked separately by an error correction and detection circuit which only checks 32 bits at a time, rather than all 64 bits of the entire data field at one time. A pair of single bit check circuits are provided for quickly determining if a single bit error will be located by the error correction and detection circuit for their respective 32 bit data portion. If either single bit check circuit determines that a single bit error will be located and corrected by the error detection and correction circuit, a clock block signal is generated to stop data processing until after the single bit error is corrected. The single bit check circuits, which operate in parallel, can thus determine if a single bit error exists in either 32 bit portion in about 31 nanoseconds. If a single bit error does exist, processing can be stopped before the bad data is used. If no single bit errors exist, the data processing system can continue with no degradation in its operation.
In addition, 32 bit data paths may be used rather than 64 bit paths. Also, less expensive, slower memory devices may be used, while still having the same or nearly the same time performance.
Memory operations are performed using 32 bit operations, wherein two 32 bit operations may be processed in parallel such that a 32 bit memory appears to be a 64 bit memory.